set test_disable_find_best_scan_out "true"
set test_dont_fix_constraint_violations "true"
set test_dedicated_subdesign_scan_outs "false"

这三句一定要加在脚本的最前面，千万不能省事的认为加载dc_setup文件中就可以了，事实证明是不行的。

加了这三句话，可以保证扫描链在串连时非常干净，中间都是上级输出直接连接到本级SI端，中间没有buf等。

还有要注意的是：

在dc的xg模式下，扫描链时钟的周期不用设置成100，如果是100，会引起串连后drc校验不过。从而引起

不能检查覆盖率，不能产生spf文件，tmax不能使用。

好像连扫描链的def文件都不能生成了。

具体原因还不清楚，以后慢慢摸索着补上。

Pls ans the following.
Is this test-ready design?
Sunil Budumuru
Added after 3 hours 38 minutes:
Dear Friend,
U can try the following flow.
read_file -format ddc mapped/compile_top.ddc
Current_design xxxxxx
Link
compile_ultra -num_cpus 4 –scan
create_port -direction "in" {Reset TEST_MODE}
Current_design xxxxxx
Link
change_names -rules verilog -verbose -hierarchy
write -f verilog -h -o mapped/scan_replaced.v
# DFT variable declaration
set test_default_period 10
set test_default_bidir_delay 0
set test_default_delay 0
set test_default_min_fault_coverage 98
set test_default_scan_style "multiplexed_flip_flop"
set test_default_strobe 4
test_stil_multiclock_capture_procedures = true
set_scan_configuration -chain_count 6 \
-add_lockup true \
-internal_clocks multi\
-clock_mixing mix_clocks \
-style multiplexed_flip_flop
##############scan path #############
set_dft_signal -view spec \
-hookup_pin [get_pins p0in_pad/DI] \
-port [get_ports Pin_PAD] \
-hookup_sense non_inverted \
-type ScanDataIn
set_dft_signal -view spec \
-hookup_pin [get_pins p0out_pad/DO] \
-port Pout_PAD \
-hookup_sense non_inverted \
-type ScanDataOut
set_scan_path chain0 -view spec \
-scan_data_in [get_ports Pin_PAD] \
-scan_data_out [get_ports Pout_PAD]
set_dft_signal -view existing_dft -type ScanClock -timing {4.5 5.5} -port clk
set_dft_signal -view existing_dft -type ScanClock -timing {4.5 5.5} -port wb_clk_lower
set_dft_signal -view existing_dft -type Reset -active 0 -port Reset
set_dft_signal -view existing_dft -type Constant -active 1 -port TEST_MODE
set_dft_signal -view existing_dft \
-port [get_ports [list TEST_MODE]] \
-hookup_sense non_inverted \
-type TestMode \
-active_state 1
set_dft_signal -view spec \
-port [get_ports [list TEST_MODE]] \
-hookup_sense non_inverted \
-type TestMode \
-active_state 1
#autofix
#set the signal to use
set_dft_signal -type TestMode -port TEST_MODE
set_dft_signal -type TestData -port clk
set_dft_signal -type TestData -port wb_clk_lower
set_dft_signal -type TestData -port Reset
set_dft_configuration \
-fix_bidirectional disable \
-scan enable \
-fix_clock enable \
-fix_set enable \
-fix_reset enable
set_autofix_configuration -type clock \
-include_elements [get_object_name [all_registers ] ] \
-method mux \
-control_signal TEST_MODE \
-test_data wb_clk_lower
set_autofix_configuration -type clock \
-include_elements [get_object_name [all_registers ] ] \
-method mux \
-control_signal TEST_MODE \
-test_data clk
set_autofix_configuration -type reset \
-method mux \
-control_signal TEST_MODE \
-test_data Reset
set_autofix_configuration -type set \
-method mux \
-control_signal TEST_MODE \
-test_data Reset
######## Test Protocal creation ######################
create_test_protocol -infer_clock -capture_procedure multi_clock
write_test_protocol -out protocol.spf
dft_drc -pre_dft -verbose > reports/dftdrc_prescan.rpt
################ preview dft ###########################
preview_dft -test_points all > reports/preview_dft_tp.rpt
preview_dft -show all > reports/preview_dft_all.rpt
################ Stritch the Scan Cells #################
insert_dft
# postscan drc
dft_drc -verbose > reports/dft_drc_postscan.rpt
# output netlist
change_names -rules verilog -verbose -hierarchy
write -f verilog -h -o output/top_postscan.vs
write_scan_def -o vpc_top.def
# coverage
estimate_test_coverage -sample 99 > reports/dft_coverage.rpt
pls update the results.
asic-dft.com
Added after 3 minutes:
once u r done with the above run, from next time onwards, u can use "scan_replaced.v"
to avoid your compile.
Just read the scan replaced netlsit and do the R&D on that.

不知道有没有大侠在Red hat enterprise 5下安装ic610的？
我在安装时遇到下面的问题：
Initializing InstallScape using JVM at /eda_soft/Cadence/InstallScape/iscape/runtime/LNX86/bin/java. This might take some time...
Exception in thread "main" java.lang.UnsatisfiedLinkError: /eda_soft/Cadence/InstallScape/iscape/runtime/LNX86/lib/i386/libawt.so: libXp.so.6: cannot open shared object file: No such file or directory

at java.lang.ClassLoader$NativeLibrary.load(Native Method)

at java.lang.ClassLoader.loadLibrary0(ClassLoader.java:1586)

at java.lang.ClassLoader.loadLibrary(ClassLoader.java:1503)

at java.lang.Runtime.loadLibrary0(Runtime.java:788)

at java.lang.System.loadLibrary(System.java:834)

at sun.security.action.LoadLibraryAction.run(LoadLibraryAction.java:50)

at java.security.AccessController.doPrivileged(Native Method)

at java.awt.Toolkit.loadLibraries(Toolkit.java:1437)

at java.awt.Toolkit.<clinit>(Toolkit.java:1458)

at com.khanpur.installer.gui.InstallerUI.main(InstallerUI.java:70)

然后就退出了，不知道如何解决？

*************************************

下载libXp.so.6安装可解决这个在RHEL5上安装ic610的问题！

**************************************

启动icfb时出现如下错误：
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 12 error 3 serial 1738
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 10 error 3 serial 1739
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 10 error 3 serial 1740
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 15 error 3 serial 1741
\o
© 1992-2006
UNIX SYSTEMS Laboratories INC.,
\e Display :0.0 Error "BadDrawable (invalid Pixmap or Window parameter)"
\e
request 62 error 9 serial 1764
\e Display :0.0 Error "BadMatch (invalid parameter attributes)"
\e
request 1 error 8 serial 1766
\e Display :0.0 Error "BadDrawable (invalid Pixmap or Window parameter)"
\e
request 155 error 9 serial 1767
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1768
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1769
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1770
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1771
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1772
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 12 error 3 serial 1773
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1774
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1775
\e Display :0.0 Error "BadWindow (invalid Window parameter)"
\e
request 18 error 3 serial 1776
不知道是什么情况？请大家指教！多谢！
******************************************

我遇到过相同的问题，好像是在xorg.conf里面加上下面一段就可以了，试试看
Section "Extensions"
Option "Composite" "Disable"
EndSection

*****************************************

果然，下载libxp
修改下Xorg.conf
重启X就好了

*******************************************
在red hat enterprise 5下安装ic610的问题,查到这样一个解决的帖子,转过来大家看看,待验证.

转自:http://bbs.stirf.com/viewthread.php?tid=12

Downloaded the Cadence IC Design - Virtuoso (Ver 6.10) from the following site:
http://www.verycd.com/topics/148755/
Installed IC610 Base on the system ubuntu 7.10 using installscape. Succeeded in intel X86 system but failed in AMD64 system.
You could install the software following the instructions from here:
http://www.et.byu.edu/groups/ece451web/cadence-help/getstarted.html
The installation is very easy, setup the environment after the installation.
export LM_LICENSE_FILE= (put here where your license server or file is located)
export CDS_LIC_FILE = (put here where your license server or file is located)
export LD_LIBRARY_PATH = (library paths of ic and ldv ic/tools/lib, ldv/tools/lib, spr/tools/lib, soc/tools/lib)
export OA_HOME = (OA installed directory)
export CDS_SITE = (location of NCSU design kit installation directory - …/NCSU/local)
export CDS_Netlisting_Mode=Analog
export USE_NCSU_CDK
export CDS = (NCSU design kit directory …/NCSU/local/cdssetup)
export PATH=$PATHall cadence tool directories that are required are listed below)

…/ic/tools/bin
…/ic/tools/dfII/bin
…/ic/tools/concice/bin
…/ic/tools/dracula/bin
…/ic/tools/plot/bin
…/ldv/tools/bin
…/spr/tools/bin
…/soc/tools/bin
…/icc/tools/iccraft/bin

The problems I’ve met when I tried to run icfb:
1. Code:
Qt Warning: X Error: BadWindow (invalid Window parameter) 3
Major opcode: 2 (X_ChangeWindowAttributes)
Resource id: 0×2e00011

and
Code:
Display :0.0 Error “BadWindow (invalid Window parameter)”
\e request 18 error 3 serial 1392
It will not be appeared when using ssh connection from windows client, so it seems to be the linux display problems. You could simply solve this promblem by adding following scripts in the /etc/X11/Xorg.conf file:
Code:
Section “Extensions”
Option “Composite” “Disable”
EndSection
2.
Quote:
/usr/local/cadence/IC610/tools/dfII/bin/icfb: 97: cds_plat: not found
/usr/local/cadence/IC610/share/oa/bin/sysname: 328: /bin/awk: not found
/usr/local/cadence/IC610/tools/dfII/bin/32bit/icfb.exe: error while loading shared libraries: libelf.so.1: cannot open shared object file: No such file or directory

Ignored the first problem first.
The sencond problem could be solved easily: make a awk link in /bin using this command
Quote:
sudo ln -s /usr/bin/awk /bin/awk
apt-cache search libelf and apt-get install libelf**
If the error still existed, make a link libelf.so.1, first find available libelf useing
Quote:
ls -l libelf*
some file name will show up, then make a link to it using
Quote:
ln -s /use/lib/ /usr/lib/libelf.so.1
In AMD64 system require liblbss.so* rather than libelf.so.1. Haven’t solved this problem yet.
Then the icfb could be started up now, but the first problem will still exist. I dont know how to solve but just adding a comment at the begin of the sentence where calling for cds_plat.
3. The other problem met: cant open online help document.
export MOZILLA_HOME=/usr/bin/netscape , but it seems not working on my machine.

[ 本帖最后由 castlerock 于 2008-8-1 18:08 编辑 ]

最近研究DFT的时候发现在产生的def文件中有大量的BUF问题。这说明串连的时候不是从

前一个触发器的Q端直接到本触发器的SI端，而是中间进过了BUF。

在ASTRO中，网表读入后，总是会先删除BUF和成对出现的INV,因此，

在ASTRO串连的时候经常会出现 找不到触发器的下一级 的问题

经过研究，找到的解决办法如下

在脚本文件的开头，添加下面的参数

set test_disable_find_best_scan_out "true"   ;#不允许寻找最佳的scan out点，直接串连触发器
set test_dont_fix_constraint_violations "true";# 不允许对串连后引起的约束告警进行修理，因为ASTRO会自己打断链，修理没有必要
set test_dedicated_subdesign_scan_outs "false" ;#禁止对子模块添加专门的测试输出口。这个是引入BUF的重要原因。

完整的脚本如下

set test_disable_find_best_scan_out "true"
set test_dont_fix_constraint_violations "true"
set test_dedicated_subdesign_scan_outs "false"

set mdir /home/source
source $mdir/script/micro.tcl

read_file -format db $mdir/netlist/mapped/$Isp_rfilename.db
set verilogout_no_tri true
set_fix_multiple_port_nets -all -buffer_constants [get_designs *]

source $mdir/script/nouse.tcl

set_scan_configuration -style multiplexed_flip_flop -clock_mixing  no_mix -internal_clocks false
set_scan_configuration -add_lockup true -chain_count 6 -dedicated_scan_ports true
set_scan_configuration -prtool avant

create_test_clock CLK -internal_clocks false -period 100 -waveform " 45 55"

set_dft_signal test_mode  -port SCAN_TEST -hookup IN02/D
set_test_hold 1 SCAN_TEST

set_scan_signal test_scan_enable -port SCAN_ENA -hookup IN04/D

set_signal_type test_asynch_inverted RESET_N

set_scan_path chain1 -insert_terminal_lockup true 

set_scan_signal test_scan_in  -port PIN_SI0 -chain chain1 -hookup IN05/D
set_scan_signal test_scan_out -port PIN_SO0 -chain chain1 -hookup OUT01/A

set_scan_path chain2 -insert_terminal_lockup true

set_scan_signal test_scan_in  -port PIN_SI1 -chain chain2  -hookup IN74/D
set_scan_signal test_scan_out -port PIN_SO1 -chain chain2  -hookup OUT38/A

set_scan_path chain3 -insert_terminal_lockup true
set_scan_signal test_scan_in  -port PIN_SI2 -chain chain3 -hookup IN75/D
set_scan_signal test_scan_out -port PIN_SO2 -chain chain3  -hookup OUT39/A

create_test_protocol

preview_dft
dft_drc

insert_dft
dft_drc -coverage_estimate
write_test_protocol -output    $mdir/netlist/mapped/$Isp_wfilename.unflatten.spf
   write_layout_scan

   define_name_rules verilog -equal_ports_nets -inout_ports_equal_nets -remove_internal_net_bus -remove_port_bus
   change_names -rules verilog -hierarchy -verbose

   write -hierarchy -f db -o      $mdir/netlist/mapped/$Isp_wfilename.db
   write -hierarchy -f verilog -o $mdir/netlist/mapped/$Isp_wfilename.v
   write_sdc                      $mdir/netlist/mapped/$Isp_wfilename.sdc

   remove_unconnected_ports -blast_buses [find cell -hierarchy * ]
   write -hierarchy -f db -o      $mdir/netlist/mapped/$Isp_wfilename.rm-uc.db
   write -hierarchy -f verilog -o $mdir/netlist/mapped/$Isp_wfilename.rm-uc.v
   write_sdc                      $mdir/netlist/mapped/$Isp_wfilename.rm-uc.sdc

exit

在综合后仿真的时候，发现时钟2选1的输出为亚稳态，

在断开时钟输出以后，2选一输出正常。由此判断是因为

输出负载过重引起。

解决办法：

重新定义时钟起始点。

起始点重新定义在2选1的输出端Y上

create_clock –name “aclk” –period 18 –waveform { 0 9}  systop/clkgen/aclk/Y

也许这种定义方法明确了时钟的起始点，

在定义复位等一类负载较大的线的时候应该也可以使用。

命令为

v1999.10 PrimeTime Commands

set_driving_cell

Sets the port driving cell.

SYNTAX

string set_driving_cell [-lib_cell lib_cell_name] [-rise] [-fall] [-min] [-max] [­library lib_name] [-pin pin_name] [-from_pin pin_name] [-multiply_by factor] [-dont_scale] [-no_design_rule] port_list stringlib_cell_name stringlib_name stringpin_name stringpin_name float factor float rtran float ftran list port_list

ARGUMENTS

-lib_cell lib_cell_name Specifies the name of the library cell used to drive the ports. If the cell has more than one output pin, -pin must be used. If different cells are needed for the rising and the falling cases, use separate commands with the -rise and -fall options. To choose between multiple input pins with arcs to this output pin, use -from_pin

-rise Sets driving_cell information for the rising port transition only.

-fall Sets driving_cell information for the falling port transition only.

-min Sets driving_cell information for the minimum analysis only. This option is only valid in min-max mode.

-max Sets driving_cell information for the minimum analysis only. This option is valid even when not in min-max mode. When not in min-max mode, the option is not required because this option is the default.

-library lib_name Specifies the name of the library where to find library_cell_name; the library of the driving cell. By default, the libraries in link_library are searched for the cell.

-pin pin_name Specifies the output pin whose drive is used; the driving pin name. If you do not specify -from_pin, an arbitrary pin arc ending at the specified pin is used.

HOME CONTENTS / 452

v1999.10 PrimeTime Commands

-from_pin pin_name Specifies an input pin on the specified cell so the drive of the timing arc from this pin to the specified pin is used.

-multiply_by factor Multiplies the calculated transition time by the specified multiplier. Transition multiplier (Range: greater than or equla to 0).

-dont_scale Prevents operating condition scaling. Indicates that the timing analyzer is not to scale the drive capability of the ports according to the current operating conditions. By default, the port drive capability is scaled for operating conditions exactly as the driving cell itself would have been scaled.

-no_design_rule Specifies not to transfer design rules from the driving cell to the port. If you do not specify this option, the design rules (such as max_capacitance) of the library pin are applied to the port.

-input_transition_rise rtranfp Specifies the input rising transition time associated with -from_pin. If this is not specified, the default value is 0. This and the -input_transition_fall option are used to capture the accurate transition time associated with ­from_pin, such that more acurate transition time and delay time at the output pin can be obtained.

-input_transition_fall ftranfp Specifies the input falling transition time associated with -from_pin. If this is not specified, the default value is 0.

port_list Provides a list of input ports. The list contains input or inout port names in the current design on which the driving cell information is set.

DESCRIPTION

Sets attributes on the specified input or inout ports in the current design to associate an external driving cell with the ports. The drive capability of the port is the same as if the specified driving cell were connected in the same context to allow accurate modeling of port drive capability for nonlinear delay models. Unless you specify -dont_scale, the drive capability of the port is scaled according to the current operating conditions.

To view drive information on ports, use report_port -drive.

The characterize_context command automatically sets driving cell information on subdesign ports based on their context in the entire design.

Use the remove_driving_cell command to remove driving cell information from ports.

Note: The set_driving_cell command removes any corresponding drive resistance or input transition attributes (from set_drive_resistance or set_input_transition) on the specified ports. If possible, always use set_driving_cell instead of

HOME CONTENTS / 453

v1999.10 PrimeTime Commands

set_drive_resistance, because set_driving_cell allows accurate calculation of port delay and transition time for library cells with nonlinear dependence on capacitance.

EXAMPLES

pt_shell> set_driving_cell -lib_cell AND [get_ports A] pt_shell> report_port -drive A

**************************************** Report : port -drive Design : counter Version: 1997.08 Date : Tue 1996 ****************************************

Resistance Transition Input Port Rise Fall Rise Fall

A -- -- -- -­

Driving Cell Input Port Rise Fall Mult Attrs

A AND AND -­

SEE ALSO

all_inputs (2), characterize_context (2), remove_driving_cell (2), report_port (2), reset_design (2), set_drive_resistance (2), set_input_transition (2), set_capacitance (2).

HOME CONTENTS / 454

实例为：

set_driving_cell –lib_cell INVX8HS –pin Y –library sagehs_smic_013g_ss_1p08v_125c [all_inputs]